GDS Flow Configuration Variables

This is an auto-generated reference of all GDS flow configuration variables used by the FABulous GDS generator.

These variables can be configured in the gds_config.yaml file located in either:

• <project>/Tile/include/gds_config.yaml - Base configuration for all tiles

• <project>/Tile/<tile_name>/gds_config.yaml - Per-tile specific configuration

• <project>/Fabric/gds_config.yaml - Fabric-level configuration

Auto Eco Diode Insertion

Variable	Type	Default	Description
RT_CLOCK_MIN_LAYER	Optional	-	The name of lowest layer to be used in routing the clock net.
RT_CLOCK_MAX_LAYER	Optional	-	The name of highest layer to be used in routing the clock net.
GRT_ADJUSTMENT	Decimal	0.3	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.
GRT_MACRO_EXTENSION	int	0	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.
GRT_LAYER_ADJUSTMENTS	List	-	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.
DIODE_PADDING	Optional	-	Diode cell padding; increases the width of diode cells during placement checks..
GRT_ALLOW_CONGESTION	bool	False	Allow congestion during global routing
GRT_ANTENNA_REPAIR_ITERS	int	3	The maximum number of iterations for global antenna repairs.
GRT_OVERFLOW_ITERS	int	50	The maximum number of iterations waiting for the overflow to reach the desired value.
GRT_ANTENNA_REPAIR_MARGIN	int	10	The margin to over fix antenna violations.
GRT_ANTENNA_REPAIR_JUMPER_ONLY	bool	False	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.
GRT_ANTENNA_REPAIR_DIODE_ONLY	bool	False	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.
PL_OPTIMIZE_MIRRORING	bool	True	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.
PL_MAX_DISPLACEMENT_X	int	500	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.
PL_MAX_DISPLACEMENT_Y	int	100	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.
DPL_CELL_PADDING	int	-	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.
INSERT_ECO_DIODES	Optional	-	List of sinks to insert diodes for.
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
AUTO_ECO_DIODE_INSERT_MODE	str	all	Mode for diode insertion, options are ‘none’, ‘ratio’ or ‘all’. ‘ratio’ inserts diodes based on the ratio of partial to required antenna area, ‘all’ inserts diodes for all violating pins, ‘none’ inserts no diodes. Default is ‘all’.

Conditional Magic DRC

Variable	Type	Default	Description
MAGIC_DEF_LABELS	bool	False	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.
MAGIC_GDS_POLYGON_SUBCELLS	bool	False	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”
MAGIC_GDS_MERGE	bool	True	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”
MAGIC_DEF_NO_BLOCKAGES	bool	True	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.
MAGIC_INCLUDE_GDS_POINTERS	bool	False	A flag to choose whether to include GDS pointers in the generated mag files or not.
MAGICRC	Path	-	A path to the .magicrc file which is sourced before running magic in the flow.
MAGIC_TECH	Path	-	A path to a Magic tech file which, mainly, has DRC rules.
MAGIC_PDK_SETUP	Path	-	A path to a PDK-specific setup file sourced by .magicrc.
CELL_MAGS	Optional	-	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.
CELL_MAGLEFS	Optional	-	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.
MAGIC_CAPTURE_ERRORS	bool	True	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.
MAGIC_DRC_USE_GDS	bool	True	A flag to choose whether to run the Magic DRC checks on GDS or not. If not, then the checks will be done on the DEF view of the design, which is a bit faster, but may be less accurate as some DEF/LEF elements are abstract.
MAGIC_GDS_FLATGLOB	Optional	-	Flatten cells by name pattern on input. May be used to avoid false positive DRC errors. The strings may use standard shell-type glob patterns, with * for any length string match, ? for any single character match, \ for special characters, and [] for matching character sets or ranges.
MAGIC_DRC_MAGLEFS	Optional	-	A list of pre-processed abstract LEF views for cells. They are read in before the design and act as blackboxes during DRC.

Diodes On Ports

Variable	Type	Default	Description
DIODE_ON_PORTS	Literal	none	Always insert diodes on ports with the specified polarities.
GPL_CELL_PADDING	int	-	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
RT_CLOCK_MIN_LAYER	Optional	-	The name of lowest layer to be used in routing the clock net.
RT_CLOCK_MAX_LAYER	Optional	-	The name of highest layer to be used in routing the clock net.
GRT_ADJUSTMENT	Decimal	0.3	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.
GRT_MACRO_EXTENSION	int	0	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.
GRT_LAYER_ADJUSTMENTS	List	-	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.
PL_OPTIMIZE_MIRRORING	bool	True	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.
PL_MAX_DISPLACEMENT_X	int	500	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.
PL_MAX_DISPLACEMENT_Y	int	100	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.
DPL_CELL_PADDING	int	-	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.
RSZ_DONT_TOUCH_RX	str	$^	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.
RSZ_DONT_TOUCH_LIST	Optional	-	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.
RSZ_CORNERS	Optional	-	Resizer step-specific override for PNR_CORNERS.
PL_TARGET_DENSITY_PCT	Optional	-	The desired placement density of cells. If not specified, the value will be equal to (FP_CORE_UTIL + 5 * GPL_CELL_PADDING + 10).
PL_SKIP_INITIAL_PLACEMENT	bool	False	Specifies whether the placer should run initial placement or not.
PL_WIRE_LENGTH_COEF	Decimal	0.25	Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths
PL_MIN_PHI_COEFFICIENT	Optional	-	Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html
PL_MAX_PHI_COEFFICIENT	Optional	-	Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html
FP_CORE_UTIL	Decimal	50	The core utilization percentage.
PL_KEEP_RESIZE_BELOW_OVERFLOW	Optional	-	Only applicable when PL_TIMING_DRIVEN is enabled. When the overflow is below the set value, timing-driven iterations will retain the resizer changes instead of reverting them. Allowed values are 0 to 1. If not set, a nonzero default value from OpenROAD will be used
PL_TIMING_DRIVEN	bool	False	Specifies whether the placer should use timing-driven placement.
PL_ROUTABILITY_DRIVEN	bool	True	Specifies whether the placer should use routability driven placement.
PL_ROUTABILITY_OVERFLOW_THRESHOLD	Optional	-	Sets overflow threshold for routability mode.

Extract PDK Info

Variable	Type	Default	Description
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
FP_FLIP_SITES	Optional	-	Flip these sites vertically. Useful in niche alignment scenarios where single-height cells have ground at the south side and double-height cells have power at the south side, causing a short. In that situation, flipping the sites for single-height cells resolves the issue.
FP_TRACKS_INFO	Path	-	A path to the a classic OpenROAD .tracks file. Used by the floorplanner to generate tracks.
FP_SIZING	Literal	relative	Sizing mode for floorplanning
FP_ASPECT_RATIO	Decimal	1	The core’s aspect ratio (height / width).
FP_CORE_UTIL	Decimal	50	The core utilization percentage.
FP_OBSTRUCTIONS	Optional	-	Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow.
PL_SOFT_OBSTRUCTIONS	Optional	-	Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area.
CORE_AREA	Optional	-	Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with DIE_AREA.
BOTTOM_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the bottom boundary. If DIEA_AREA and CORE_AREA are set, this variable has no effect.
TOP_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the top boundary. If DIE_AREA and CORE_AREA are set, this variable has no effect.
LEFT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the left boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
RIGHT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the right boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
EXTRA_SITES	Optional	-	Explicitly specify sites other than PLACE_SITE to create rows for. If the alternate-site standard cells properly declare the SITE property, you do not need to provide this explicitly.

Fabric

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
FABULOUS_TILE_SPACING	Union	(0, 0)	The spacing between tiles. Either a scalar (applied to both axes) or (x_spacing, y_spacing).
FABULOUS_HALO_SPACING	Union	(0, 0, 0, 0)	The spacing around the fabric. Either a scalar (applied to all four sides) or [left, bottom, right, top].
FABULOUS_SPEF_CORNERS	list	[‘nom’]	The SPEF corners to use for the tile macros.
IO_PIN_H_LAYER	str	-	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.
IO_PIN_V_LAYER	str	-	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.
IO_PIN_V_EXTENSION	Decimal	0	Extends the vertical io pins outside of the die by the specified units.
IO_PIN_H_EXTENSION	Decimal	0	Extends the horizontal io pins outside of the die by the specified units.
IO_PIN_V_THICKNESS_MULT	Decimal	2	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.
IO_PIN_H_THICKNESS_MULT	Decimal	2	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.
IO_PIN_V_LENGTH	Optional	-	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
IO_PIN_H_LENGTH	Optional	-	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
FABULOUS_FABRIC_CONFIG	list	-	Path to the fabric CSV describing the tile map, parameters, and per-tile CSV locations.
FABULOUS_TILE_LIBRARY	list	-	List of paths to the tile library roots.
FABULOUS_TILE_MACROS	dict[str, pathlib.Path]	None	-

Fabric Macro Flow

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
FABULOUS_TILE_SPACING	Union	(0, 0)	The spacing between tiles. Either a scalar (applied to both axes) or (x_spacing, y_spacing).
FABULOUS_HALO_SPACING	Union	(0, 0, 0, 0)	The spacing around the fabric. Either a scalar (applied to all four sides) or [left, bottom, right, top].
FABULOUS_SPEF_CORNERS	list	[‘nom’]	The SPEF corners to use for the tile macros.
IO_PIN_H_LAYER	str	-	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.
IO_PIN_V_LAYER	str	-	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.
IO_PIN_V_EXTENSION	Decimal	0	Extends the vertical io pins outside of the die by the specified units.
IO_PIN_H_EXTENSION	Decimal	0	Extends the horizontal io pins outside of the die by the specified units.
IO_PIN_V_THICKNESS_MULT	Decimal	2	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.
IO_PIN_H_THICKNESS_MULT	Decimal	2	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.
IO_PIN_V_LENGTH	Optional	-	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
IO_PIN_H_LENGTH	Optional	-	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width

Fabric Macro Full Flow

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
FP_FLIP_SITES	Optional	-	Flip these sites vertically. Useful in niche alignment scenarios where single-height cells have ground at the south side and double-height cells have power at the south side, causing a short. In that situation, flipping the sites for single-height cells resolves the issue.
FP_TRACKS_INFO	Path	-	A path to the a classic OpenROAD .tracks file. Used by the floorplanner to generate tracks.
FP_SIZING	Literal	relative	Sizing mode for floorplanning
FP_ASPECT_RATIO	Decimal	1	The core’s aspect ratio (height / width).
FP_CORE_UTIL	Decimal	50	The core utilization percentage.
FP_OBSTRUCTIONS	Optional	-	Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow.
PL_SOFT_OBSTRUCTIONS	Optional	-	Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area.
CORE_AREA	Optional	-	Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with DIE_AREA.
BOTTOM_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the bottom boundary. If DIEA_AREA and CORE_AREA are set, this variable has no effect.
TOP_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the top boundary. If DIE_AREA and CORE_AREA are set, this variable has no effect.
LEFT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the left boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
RIGHT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the right boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
EXTRA_SITES	Optional	-	Explicitly specify sites other than PLACE_SITE to create rows for. If the alternate-site standard cells properly declare the SITE property, you do not need to provide this explicitly.
STD_CELL_LIBRARY	str	-	Specifies the default standard cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
VDD_PIN	str	-	The power pin for the cells.
GND_PIN	str	-	The ground pin for the cells.
TECH_LEFS	Dict	-	Map of corner patterns to technology LEF files. A corner not matched here will not be supported by OpenRCX in the default flow.
PRIMARY_GDSII_STREAMOUT_TOOL	str	-	Specify the primary GDSII streamout tool for this PDK. For most open-source PDKs, that would be ‘magic’.
DEFAULT_MAX_TRAN	Optional	-	Defines the default maximum transition value used in Synthesis and CTS. A minimum of 0.1 * CLOCK_PERIOD and this variable, if defined, is used.
DEFAULT_CORNER	str	-	The interconnect/process/voltage/temperature corner (IPVT) to use the characterized lib files compatible with by default.
STA_CORNERS	List	-	A list of fully qualified IPVT (Interconnect, transistor Process, Voltage, and Temperature) timing corners on which to conduct multi-corner static timing analysis.
RT_MIN_LAYER	str	-	The lowest metal layer to route on.
RT_MAX_LAYER	str	-	The highest metal layer to route on.
SCL_GROUND_PINS	List	-	SCL-specific ground pins
SCL_POWER_PINS	List	-	SCL-specific power pins
TRISTATE_CELLS	Optional	-	A list of cell names or wildcards of tri-state buffers.
FILL_CELLS	List	-	A list of cell names or wildcards of fill cells to be used in fill insertion.
DECAP_CELLS	List	-	A list of cell names or wildcards of decap cells to be used in fill insertion.
LIB	Dict	-	A map from corner patterns to a list of associated liberty files. Exactly one entry must match the DEFAULT_CORNER.
CELL_LEFS	List	-	Path(s) to the cells’ LEF file(s).
CELL_GDS	List	-	Path(s) to the cells’ GDSII file(s).
CELL_VERILOG_MODELS	Optional	-	Path(s) to cells’ Verilog model(s)
CELL_BB_VERILOG_MODELS	Optional	-	Path(s) to cells’ black-box Verilog model(s)
CELL_SPICE_MODELS	Optional	-	Path(s) to cells’ SPICE model(s)
CELL_CDLS	Optional	-	A circuit-design language view of the standard cell library.
SYNTH_EXCLUDED_CELL_FILE	Path	-	Path to a text file containing a list of (wildcards matching) cells to be excluded from the lib file in synthesis alone.
PNR_EXCLUDED_CELL_FILE	Path	-	Path to a text file containing a list of undesirable or bad (DRC-failed or complex pinout) cells or wildcards matching cells to be excluded from synthesis AND PnR.
OUTPUT_CAP_LOAD	Decimal	-	Defines the capacitive load on the output ports.
MAX_FANOUT_CONSTRAINT	int	-	The max load that the output ports can drive to be used as a constraint on Synthesis and CTS.
MAX_TRANSITION_CONSTRAINT	Optional	-	The max transition time (slew) from high to low or low to high on cell inputs in ns to be used as a constraint on Synthesis and CTS. If not provided, it is calculated at runtime as 10% of the provided clock period, unless that exceeds the PDK’s DEFAULT_MAX_TRAN value.
MAX_CAPACITANCE_CONSTRAINT	Optional	-	The maximum capacitance constraint. If not provided, the constraint is not set in the SDC file which will fall back to the value set by the liberty file
CLOCK_UNCERTAINTY_CONSTRAINT	Decimal	-	Specifies a value for the clock uncertainty/jitter for timing analysis.
CLOCK_TRANSITION_CONSTRAINT	Decimal	-	Specifies a value for the clock transition/slew for timing analysis.
TIME_DERATING_CONSTRAINT	Decimal	-	Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing.
IO_DELAY_CONSTRAINT	Decimal	-	Specifies the percentage of the clock period used in the input/output delays.
SYNTH_DRIVING_CELL	str	-	The cell to drive the input ports, used in synthesis and static timing analysis, in the format {cell}/{port}.
SYNTH_CLK_DRIVING_CELL	Optional	-	The cell to drive the clock input ports, used in synthesis and static timing analysis, in the format {cell}/{port}. If not specified, SYNTH_DRIVING_CELL will be used.
SYNTH_TIEHI_CELL	str	-	Defines the tie high cell followed by the port that implements the tie high functionality, in the format {cell}/{port}.
SYNTH_TIELO_CELL	str	-	Defines the tie high cell followed by the port that implements the tie low functionality, in the format {cell}/{port}.
SYNTH_BUFFER_CELL	str	-	Defines a buffer port to be used by yosys during synthesis: in the format {cell}/{input_port}/{output_port}
PLACE_SITE	str	-	Defines the primary placement site in placement as specified in the technology LEF files, to generate the placement grid.
CELL_PAD_EXCLUDE	List	-	Defines a list of cells to be excluded from cell padding.
DIODE_CELL	Optional	-	Defines a diode cell used to fix antenna violations, in the format {cell}/{port}. If not defined, steps should not attempt to repair the antenna effect by inserting diode cells.
WELLTAP_CELL	Optional	-	Defines the cell used for tap insertion. If not defined, steps should not attempt to insert welltap cells.
ENDCAP_CELL	Optional	-	Defines the so-called ‘end-cap’ cell- class of decap cells placed at either sides of a design, if available.
DESIGN_DIR	Path	-	The directory of the design. Should be set via command-line arguments or :meth:Config.load flags and not actual configuration files. If using a configuration file, DESIGN_DIR will be the directory where that file exists.
PDK_ROOT	Path	-	The home path of all PDKs. Should be set via command-line arguments or :meth:Config.load flags and not actual configuration files.
DESIGN_NAME	str	-	The name of the top level module of the design. Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
PDK	str	sky130A	Specifies the process design kit (PDK). Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
CLOCK_PERIOD	Decimal	10.0	The clock period for the design.
CLOCK_PORT	Union	-	The name(s) of the design’s clock port(s).
CLOCK_NET	Union	-	The name of the net input to root clock buffer. If unset, it is presumed to be equal to CLOCK_PORT.
VDD_NETS	Optional	-	Specifies the power nets/pins to be used when creating the power grid for the design.
GND_NETS	Optional	-	Specifies the ground nets/pins to be used when creating the power grid for the design.
DIE_AREA	Optional	-	Specific die area to be used in floorplanning. Specified as a 4-corner rectangle “x0 y0 x1 y1”.
EXTRA_EXCLUDED_CELLS	Optional	-	Wildcards matching additional cells to exclude from both synthesis and PnR.
MACROS	Optional	-	A dictionary of Macro definition objects. See librelane.config.Macro for more info.
EXTRA_LEFS	Optional	-	Specifies miscellaneous LEF files to be loaded indiscriminately whenever LEFs are loaded.
EXTRA_VERILOG_MODELS	Optional	-	Specifies miscellaneous Verilog models to be loaded indiscriminately during synthesis.
EXTRA_SPICE_MODELS	Optional	-	Specifies miscellaneous SPICE models to be loaded indiscriminately whenever SPICE models are loaded.
EXTRA_CDLS	Optional	-	Specifies miscellaneous CDL netlists to be loaded indiscriminately whenever CDL netlists are loaded.
EXTRA_LIBS	Optional	-	Specifies LIB files of pre-hardened macros used in the current design, used during timing analyses (and during parasitics-based STA as a fallback). These are loaded indiscriminately for all timing corners.
EXTRA_GDS	Optional	-	Specifies GDS files of pre-hardened macros used in the current design, used during tape-out.
FALLBACK_SDC	Path	<resource>/base.sdc	A fallback SDC file for when a step-specific SDC file is not defined.
PAD_GDS	Optional	-	Path(s) to IO pad GDS file(s).
PAD_LEFS	Optional	-	Path(s) to IO pad LEF file(s).
PAD_VERILOG_MODELS	Optional	-	Path(s) to IO pads’ Verilog model(s)
PAD_SPICE_MODELS	Optional	-	Path(s) to IO pads’ SPICE model(s)
PAD_CDLS	Optional	-	A circuit-design language view of the io pad library.
PAD_LIBS	Optional	-	A map from corner patterns to a list of associated liberty files. Exactly one entry must match the DEFAULT_CORNER.
PAD_CORNER	Optional	-	The pad corner cell.
PAD_FILLERS	Optional	-	A list of pad filler cells.
PAD_SITE_NAME	Optional	-	Name of the pad site.
PAD_CORNER_SITE_NAME	Optional	-	Name of the corner site.
PAD_FAKE_SITES	Optional	-	A dict of fake pad sites and their width and height tuple. Use this if the LEF does not include the site definitions for the IO pads.
PAD_BONDPAD_NAME	Optional	-	Name of the bondpad cell, if empty, bondpads won’t be placed.
PAD_BONDPAD_WIDTH	Optional	-	Width of the bondpad.
PAD_BONDPAD_HEIGHT	Optional	-	Height of the bondpad.
PAD_BONDPAD_OFFSETS	Optional	-	A dict of pad master names or regular expressions to their bondpad (offset_x, offset_y) tuple.
PAD_PLACE_IO_TERMINALS	Optional	-	Place I/O terminals for these master/pin combinations.
PAD_EDGE_SPACING	Optional	0	Distance from the padring to the die boundary. Used to account for the sealring when placing the pads.
TILE_OPT_INFO	Optional	-	Tile optimization information dictionary or path to JSON file
FABULOUS_FABRIC	Fabric	-	Fabric configuration object
FABULOUS_PROJ_DIR	Path	-	Path to the FABulous project directory
FABULOUS_NLP_FTOL_TOLERANCE	float	1e-06	Function tolerance for NLP optimizer - stops when objective change is below this value

Generate PDN

Variable	Type	Default	Description
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
PDN_SKIPTRIM	bool	False	Enables -skip_trim option during pdngen which skips the metal trim step, which attempts to remove metal stubs.
PDN_CORE_RING	bool	False	Enables adding a core ring around the design. More details on the control variables in the PDK config documentation.
PDN_ENABLE_RAILS	bool	True	Enables the creation of rails in the power grid.
PDN_HORIZONTAL_HALO	Decimal	10	Sets the horizontal halo around the macros during power grid insertion.
PDN_VERTICAL_HALO	Decimal	10	Sets the vertical halo around the macros during power grid insertion.
PDN_MULTILAYER	bool	True	Controls the layers used in the power grid. If set to false, only the lower layer will be used, which is useful when hardening a macro for integrating into a larger top-level design.
PDN_RAIL_OFFSET	Decimal	-	The offset for the power distribution network rails for first metal layer.
PDN_VWIDTH	Decimal	-	The strap width for the vertical layer in generated power distribution networks.
PDN_HWIDTH	Decimal	-	The strap width for the horizontal layer in generated power distribution networks.
PDN_VSPACING	Decimal	-	Intra-spacing (within a set) of vertical straps in generated power distribution networks.
PDN_HSPACING	Decimal	-	Intra-spacing (within a set) of horizontal straps in generated power distribution networks.
PDN_VPITCH	Decimal	-	Inter-distance (between sets) of vertical power straps in generated power distribution networks.
PDN_HPITCH	Decimal	-	Inter-distance (between sets) of horizontal power straps in generated power distribution networks.
PDN_VOFFSET	Decimal	-	Initial offset for sets of vertical power straps.
PDN_HOFFSET	Decimal	-	Initial offset for sets of horizontal power straps.
PDN_CORE_RING_VWIDTH	Decimal	-	The width for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HWIDTH	Decimal	-	The width for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VSPACING	Decimal	-	The spacing for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HSPACING	Decimal	-	The spacing for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VOFFSET	Decimal	-	The offset for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HOFFSET	Decimal	-	The offset for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_CONNECT_TO_PADS	bool	False	If specified, the core side of the pad pins will be connected to the ring.
PDN_CORE_RING_ALLOW_OUT_OF_DIE	bool	True	If specified, the ring shapes are allowed to be outside the die boundary.
PDN_RAIL_LAYER	str	-	Defines the metal layer used for PDN rails.
PDN_RAIL_WIDTH	Decimal	-	Defines the width of PDN rails on the PDN_RAIL_LAYER layer.
PDN_HORIZONTAL_LAYER	str	-	Defines the horizontal PDN layer.
PDN_VERTICAL_LAYER	str	-	Defines the vertical PDN layer.
PDN_CORE_HORIZONTAL_LAYER	Optional	-	Defines the horizontal PDN layer for the core ring. Falls back to PDN_HORIZONTAL_LAYER if undefined.
PDN_CORE_VERTICAL_LAYER	Optional	-	Defines the vertical PDN layer for the core ring. Falls back to PDN_VERTICAL_LAYER if undefined.
PDN_EXTEND_TO	Literal	core_ring	Defines how far the stripes and rings extend.
PDN_ENABLE_PINS	bool	True	If specified, the power straps will be promoted to block pins.
PDN_CFG	Optional	<resource>/pdn_config.tcl	A custom PDN configuration file. If not provided, the default PDN config will be used. This default config is a custom config that differ from the librelane default.

Global Tile Size Optimization

Variable	Type	Default	Description
TILE_OPT_INFO	Optional	-	Tile optimization information dictionary or path to JSON file
FABULOUS_FABRIC	Fabric	-	Fabric configuration object
FABULOUS_PROJ_DIR	Path	-	Path to the FABulous project directory
FABULOUS_NLP_FTOL_TOLERANCE	float	1e-06	Function tolerance for NLP optimizer - stops when objective change is below this value

PDN

Variable	Type	Default	Description
PDN_SKIPTRIM	bool	False	Enables -skip_trim option during pdngen which skips the metal trim step, which attempts to remove metal stubs.
PDN_CORE_RING	bool	False	Enables adding a core ring around the design. More details on the control variables in the PDK config documentation.
PDN_ENABLE_RAILS	bool	True	Enables the creation of rails in the power grid.
PDN_HORIZONTAL_HALO	Decimal	10	Sets the horizontal halo around the macros during power grid insertion.
PDN_VERTICAL_HALO	Decimal	10	Sets the vertical halo around the macros during power grid insertion.
PDN_MULTILAYER	bool	True	Controls the layers used in the power grid. If set to false, only the lower layer will be used, which is useful when hardening a macro for integrating into a larger top-level design.
PDN_RAIL_OFFSET	Decimal	-	The offset for the power distribution network rails for first metal layer.
PDN_VWIDTH	Decimal	-	The strap width for the vertical layer in generated power distribution networks.
PDN_HWIDTH	Decimal	-	The strap width for the horizontal layer in generated power distribution networks.
PDN_VSPACING	Decimal	-	Intra-spacing (within a set) of vertical straps in generated power distribution networks.
PDN_HSPACING	Decimal	-	Intra-spacing (within a set) of horizontal straps in generated power distribution networks.
PDN_VPITCH	Decimal	-	Inter-distance (between sets) of vertical power straps in generated power distribution networks.
PDN_HPITCH	Decimal	-	Inter-distance (between sets) of horizontal power straps in generated power distribution networks.
PDN_VOFFSET	Decimal	-	Initial offset for sets of vertical power straps.
PDN_HOFFSET	Decimal	-	Initial offset for sets of horizontal power straps.
PDN_CORE_RING_VWIDTH	Decimal	-	The width for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HWIDTH	Decimal	-	The width for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VSPACING	Decimal	-	The spacing for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HSPACING	Decimal	-	The spacing for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VOFFSET	Decimal	-	The offset for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HOFFSET	Decimal	-	The offset for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_CONNECT_TO_PADS	bool	False	If specified, the core side of the pad pins will be connected to the ring.
PDN_CORE_RING_ALLOW_OUT_OF_DIE	bool	True	If specified, the ring shapes are allowed to be outside the die boundary.
PDN_RAIL_LAYER	str	-	Defines the metal layer used for PDN rails.
PDN_RAIL_WIDTH	Decimal	-	Defines the width of PDN rails on the PDN_RAIL_LAYER layer.
PDN_HORIZONTAL_LAYER	str	-	Defines the horizontal PDN layer.
PDN_VERTICAL_LAYER	str	-	Defines the vertical PDN layer.
PDN_CORE_HORIZONTAL_LAYER	Optional	-	Defines the horizontal PDN layer for the core ring. Falls back to PDN_HORIZONTAL_LAYER if undefined.
PDN_CORE_VERTICAL_LAYER	Optional	-	Defines the vertical PDN layer for the core ring. Falls back to PDN_VERTICAL_LAYER if undefined.
PDN_EXTEND_TO	Literal	core_ring	Defines how far the stripes and rings extend.
PDN_ENABLE_PINS	bool	True	If specified, the power straps will be promoted to block pins.
DESIGN_DIR	Path	-	The directory of the design. Should be set via command-line arguments or :meth:Config.load flags and not actual configuration files. If using a configuration file, DESIGN_DIR will be the directory where that file exists.
PDK_ROOT	Path	-	The home path of all PDKs. Should be set via command-line arguments or :meth:Config.load flags and not actual configuration files.
DESIGN_NAME	str	-	The name of the top level module of the design. Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
PDK	str	sky130A	Specifies the process design kit (PDK). Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.
CLOCK_PERIOD	Decimal	10.0	The clock period for the design.
CLOCK_PORT	Union	-	The name(s) of the design’s clock port(s).
CLOCK_NET	Union	-	The name of the net input to root clock buffer. If unset, it is presumed to be equal to CLOCK_PORT.
VDD_NETS	Optional	-	Specifies the power nets/pins to be used when creating the power grid for the design.
GND_NETS	Optional	-	Specifies the ground nets/pins to be used when creating the power grid for the design.
DIE_AREA	Optional	-	Specific die area to be used in floorplanning. Specified as a 4-corner rectangle “x0 y0 x1 y1”.
EXTRA_EXCLUDED_CELLS	Optional	-	Wildcards matching additional cells to exclude from both synthesis and PnR.
MACROS	Optional	-	A dictionary of Macro definition objects. See librelane.config.Macro for more info.
EXTRA_LEFS	Optional	-	Specifies miscellaneous LEF files to be loaded indiscriminately whenever LEFs are loaded.
EXTRA_VERILOG_MODELS	Optional	-	Specifies miscellaneous Verilog models to be loaded indiscriminately during synthesis.
EXTRA_SPICE_MODELS	Optional	-	Specifies miscellaneous SPICE models to be loaded indiscriminately whenever SPICE models are loaded.
EXTRA_CDLS	Optional	-	Specifies miscellaneous CDL netlists to be loaded indiscriminately whenever CDL netlists are loaded.
EXTRA_LIBS	Optional	-	Specifies LIB files of pre-hardened macros used in the current design, used during timing analyses (and during parasitics-based STA as a fallback). These are loaded indiscriminately for all timing corners.
EXTRA_GDS	Optional	-	Specifies GDS files of pre-hardened macros used in the current design, used during tape-out.
FALLBACK_SDC	Path	<resource>/base.sdc	A fallback SDC file for when a step-specific SDC file is not defined.
VDD_PIN	str	-	The power pin for the cells.
GND_PIN	str	-	The ground pin for the cells.

Round Die Area

Variable	Type	Default	Description
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
FP_FLIP_SITES	Optional	-	Flip these sites vertically. Useful in niche alignment scenarios where single-height cells have ground at the south side and double-height cells have power at the south side, causing a short. In that situation, flipping the sites for single-height cells resolves the issue.
FP_TRACKS_INFO	Path	-	A path to the a classic OpenROAD .tracks file. Used by the floorplanner to generate tracks.
FP_SIZING	Literal	relative	Sizing mode for floorplanning
FP_ASPECT_RATIO	Decimal	1	The core’s aspect ratio (height / width).
FP_CORE_UTIL	Decimal	50	The core utilization percentage.
FP_OBSTRUCTIONS	Optional	-	Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow.
PL_SOFT_OBSTRUCTIONS	Optional	-	Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area.
CORE_AREA	Optional	-	Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with DIE_AREA.
BOTTOM_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the bottom boundary. If DIEA_AREA and CORE_AREA are set, this variable has no effect.
TOP_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the top boundary. If DIE_AREA and CORE_AREA are set, this variable has no effect.
LEFT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the left boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
RIGHT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the right boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
EXTRA_SITES	Optional	-	Explicitly specify sites other than PLACE_SITE to create rows for. If the alternate-site standard cells properly declare the SITE property, you do not need to provide this explicitly.

Tile

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
FABULOUS_IGNORE_DEFAULT_DIE_AREA	bool	False	When is true will ignore the provided die area and use the default one instead.
FABULOUS_TILE_DIR	list	-	Path to the tile directory containing the tile CSV (<tile_name>.csv) and its associated Verilog sources. Declared as list[Path] so LibreLane’s dir::. / refg:: resolvers validate cleanly; only the first element is used.
FABULOUS_EXTERNAL_SIDE	Optional	-	The side of the macro at which the external pins are placed. The pin-ordering YAML is generated from the tile’s position in the parent fabric when available, so this value is a fallback for standalone plugin tile runs.
FABULOUS_SUPERTILE	bool	None	False

Tile IO Placement

Variable	Type	Default	Description
IO_PIN_H_LAYER	str	-	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.
IO_PIN_V_LAYER	str	-	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.
IO_PIN_V_EXTENSION	Decimal	0	Extends the vertical io pins outside of the die by the specified units.
IO_PIN_H_EXTENSION	Decimal	0	Extends the horizontal io pins outside of the die by the specified units.
IO_PIN_V_THICKNESS_MULT	Decimal	2	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.
IO_PIN_H_THICKNESS_MULT	Decimal	2	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.
IO_PIN_V_LENGTH	Optional	-	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
IO_PIN_H_LENGTH	Optional	-	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
FABULOUS_IO_PIN_ORDER_CFG	Optional	-	Path to a custom pin configuration file.
ERRORS_ON_UNMATCHED_IO	Literal	unmatched_design	Controls whether to emit an error in: no situation, when pins exist in the design that do not exist in the config file, when pins exist in the config file that do not exist in the design, and both respectively. both is recommended, as the default is only for backwards compatibility with librelane 1.

Tile Optimisation

Variable	Type	Default	Description
PNR_CORNERS	Optional	-	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for STA_CORNERS from the PDK will be used.
SET_RC_VERBOSE	bool	False	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.
LAYERS_RC	Optional	-	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.
VIAS_R	Optional	-	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.
SIGNAL_WIRE_RC_LAYERS	Optional	-	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
CLOCK_WIRE_RC_LAYERS	Optional	-	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.
PDN_CONNECT_MACROS_TO_GRID	bool	True	Enables the connection of macros to the top level power grid.
PDN_MACRO_CONNECTIONS	Optional	-	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names <instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>.
PDN_ENABLE_GLOBAL_CONNECTIONS	bool	True	Enables the creation of global connections in PDN generation.
PNR_SDC_FILE	Optional	-	Specifies the SDC file used during all implementation (PnR) steps
STA_EXTRA_CORNER_TCL_FILE	Optional	-	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.
DEDUPLICATE_CORNERS	bool	False	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.
FP_FLIP_SITES	Optional	-	Flip these sites vertically. Useful in niche alignment scenarios where single-height cells have ground at the south side and double-height cells have power at the south side, causing a short. In that situation, flipping the sites for single-height cells resolves the issue.
FP_TRACKS_INFO	Path	-	A path to the a classic OpenROAD .tracks file. Used by the floorplanner to generate tracks.
FP_SIZING	Literal	relative	Sizing mode for floorplanning
FP_ASPECT_RATIO	Decimal	1	The core’s aspect ratio (height / width).
FP_CORE_UTIL	Decimal	50	The core utilization percentage.
FP_OBSTRUCTIONS	Optional	-	Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow.
PL_SOFT_OBSTRUCTIONS	Optional	-	Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area.
CORE_AREA	Optional	-	Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with DIE_AREA.
BOTTOM_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the bottom boundary. If DIEA_AREA and CORE_AREA are set, this variable has no effect.
TOP_MARGIN_MULT	Decimal	4	The core margin, in multiples of site heights, from the top boundary. If DIE_AREA and CORE_AREA are set, this variable has no effect.
LEFT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the left boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
RIGHT_MARGIN_MULT	Decimal	12	The core margin, in multiples of site widths, from the right boundary. If DIE_AREA are CORE_AREA are set, this variable has no effect.
EXTRA_SITES	Optional	-	Explicitly specify sites other than PLACE_SITE to create rows for. If the alternate-site standard cells properly declare the SITE property, you do not need to provide this explicitly.
MACRO_PLACEMENT_CFG	Optional	-	Path to an optional override for instance placement instead of the MACROS object for compatibility with LibreLane 1. If both are None, this step is skipped.
FP_MACRO_HORIZONTAL_HALO	Decimal	10	Specify the horizontal halo size around macros.
FP_MACRO_VERTICAL_HALO	Decimal	10	Specify the vertical halo size around macros.
FP_PRUNE_THRESHOLD	Optional	-	If specified, all rows smaller in width than this value will be removed. This helps avoid “islets” of cells that are hard to route and connect to PDNs.
FP_TAPCELL_DIST	Optional	-	The distance between tap cell columns. Must be specified if WELLTAP_CELL is specified.
PDN_OBSTRUCTIONS	Optional	-	Add routing obstructions to the design before PDN stage. If set to None, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury,.
PDN_SKIPTRIM	bool	False	Enables -skip_trim option during pdngen which skips the metal trim step, which attempts to remove metal stubs.
PDN_CORE_RING	bool	False	Enables adding a core ring around the design. More details on the control variables in the PDK config documentation.
PDN_ENABLE_RAILS	bool	True	Enables the creation of rails in the power grid.
PDN_HORIZONTAL_HALO	Decimal	10	Sets the horizontal halo around the macros during power grid insertion.
PDN_VERTICAL_HALO	Decimal	10	Sets the vertical halo around the macros during power grid insertion.
PDN_MULTILAYER	bool	True	Controls the layers used in the power grid. If set to false, only the lower layer will be used, which is useful when hardening a macro for integrating into a larger top-level design.
PDN_RAIL_OFFSET	Decimal	-	The offset for the power distribution network rails for first metal layer.
PDN_VWIDTH	Decimal	-	The strap width for the vertical layer in generated power distribution networks.
PDN_HWIDTH	Decimal	-	The strap width for the horizontal layer in generated power distribution networks.
PDN_VSPACING	Decimal	-	Intra-spacing (within a set) of vertical straps in generated power distribution networks.
PDN_HSPACING	Decimal	-	Intra-spacing (within a set) of horizontal straps in generated power distribution networks.
PDN_VPITCH	Decimal	-	Inter-distance (between sets) of vertical power straps in generated power distribution networks.
PDN_HPITCH	Decimal	-	Inter-distance (between sets) of horizontal power straps in generated power distribution networks.
PDN_VOFFSET	Decimal	-	Initial offset for sets of vertical power straps.
PDN_HOFFSET	Decimal	-	Initial offset for sets of horizontal power straps.
PDN_CORE_RING_VWIDTH	Decimal	-	The width for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HWIDTH	Decimal	-	The width for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VSPACING	Decimal	-	The spacing for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HSPACING	Decimal	-	The spacing for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_VOFFSET	Decimal	-	The offset for the vertical layer in the core ring of generated power distribution networks.
PDN_CORE_RING_HOFFSET	Decimal	-	The offset for the horizontal layer in the core ring of generated power distribution networks.
PDN_CORE_RING_CONNECT_TO_PADS	bool	False	If specified, the core side of the pad pins will be connected to the ring.
PDN_CORE_RING_ALLOW_OUT_OF_DIE	bool	True	If specified, the ring shapes are allowed to be outside the die boundary.
PDN_RAIL_LAYER	str	-	Defines the metal layer used for PDN rails.
PDN_RAIL_WIDTH	Decimal	-	Defines the width of PDN rails on the PDN_RAIL_LAYER layer.
PDN_HORIZONTAL_LAYER	str	-	Defines the horizontal PDN layer.
PDN_VERTICAL_LAYER	str	-	Defines the vertical PDN layer.
PDN_CORE_HORIZONTAL_LAYER	Optional	-	Defines the horizontal PDN layer for the core ring. Falls back to PDN_HORIZONTAL_LAYER if undefined.
PDN_CORE_VERTICAL_LAYER	Optional	-	Defines the vertical PDN layer for the core ring. Falls back to PDN_VERTICAL_LAYER if undefined.
PDN_EXTEND_TO	Literal	core_ring	Defines how far the stripes and rings extend.
PDN_ENABLE_PINS	bool	True	If specified, the power straps will be promoted to block pins.
PDN_CFG	Optional	<resource>/pdn_config.tcl	A custom PDN configuration file. If not provided, the default PDN config will be used. This default config is a custom config that differ from the librelane default.
ROUTING_OBSTRUCTIONS	Optional	-	Add routing obstructions to the design. If set to None, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury.
IO_PIN_H_LAYER	str	-	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.
IO_PIN_V_LAYER	str	-	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.
IO_PIN_V_EXTENSION	Decimal	0	Extends the vertical io pins outside of the die by the specified units.
IO_PIN_H_EXTENSION	Decimal	0	Extends the horizontal io pins outside of the die by the specified units.
IO_PIN_V_THICKNESS_MULT	Decimal	2	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.
IO_PIN_H_THICKNESS_MULT	Decimal	2	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.
IO_PIN_V_LENGTH	Optional	-	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
IO_PIN_H_LENGTH	Optional	-	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width
FABULOUS_IO_PIN_ORDER_CFG	Optional	-	Path to a custom pin configuration file.
ERRORS_ON_UNMATCHED_IO	Literal	unmatched_design	Controls whether to emit an error in: no situation, when pins exist in the design that do not exist in the config file, when pins exist in the config file that do not exist in the design, and both respectively. both is recommended, as the default is only for backwards compatibility with librelane 1.
FP_DEF_TEMPLATE	Optional	-	Points to the DEF file to be used as a template.
FP_TEMPLATE_MATCH_MODE	Literal	strict	Whether to require that the pin set of the DEF template and the design should be identical. In permissive mode, pins that are in the design and not in the template will be excluded, and vice versa.
FP_TEMPLATE_COPY_POWER_PINS	bool	False	Whether to always copy all power pins from the DEF template to the design.
DIODE_ON_PORTS	Literal	none	Always insert diodes on ports with the specified polarities.
GPL_CELL_PADDING	int	-	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.
RT_CLOCK_MIN_LAYER	Optional	-	The name of lowest layer to be used in routing the clock net.
RT_CLOCK_MAX_LAYER	Optional	-	The name of highest layer to be used in routing the clock net.
GRT_ADJUSTMENT	Decimal	0.3	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.
GRT_MACRO_EXTENSION	int	0	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.
GRT_LAYER_ADJUSTMENTS	List	-	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.
PL_OPTIMIZE_MIRRORING	bool	True	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.
PL_MAX_DISPLACEMENT_X	int	500	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.
PL_MAX_DISPLACEMENT_Y	int	100	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.
DPL_CELL_PADDING	int	-	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.
RSZ_DONT_TOUCH_RX	str	$^	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.
RSZ_DONT_TOUCH_LIST	Optional	-	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.
RSZ_CORNERS	Optional	-	Resizer step-specific override for PNR_CORNERS.
PL_TARGET_DENSITY_PCT	Optional	-	The desired placement density of cells. If not specified, the value will be equal to (FP_CORE_UTIL + 5 * GPL_CELL_PADDING + 10).
PL_SKIP_INITIAL_PLACEMENT	bool	False	Specifies whether the placer should run initial placement or not.
PL_WIRE_LENGTH_COEF	Decimal	0.25	Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths
PL_MIN_PHI_COEFFICIENT	Optional	-	Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html
PL_MAX_PHI_COEFFICIENT	Optional	-	Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html
PL_KEEP_RESIZE_BELOW_OVERFLOW	Optional	-	Only applicable when PL_TIMING_DRIVEN is enabled. When the overflow is below the set value, timing-driven iterations will retain the resizer changes instead of reverting them. Allowed values are 0 to 1. If not set, a nonzero default value from OpenROAD will be used
PL_TIMING_DRIVEN	bool	False	Specifies whether the placer should use timing-driven placement.
PL_ROUTABILITY_DRIVEN	bool	True	Specifies whether the placer should use routability driven placement.
PL_ROUTABILITY_OVERFLOW_THRESHOLD	Optional	-	Sets overflow threshold for routability mode.
DIODE_PADDING	Optional	-	Diode cell padding; increases the width of diode cells during placement checks..
GRT_ALLOW_CONGESTION	bool	False	Allow congestion during global routing
GRT_ANTENNA_REPAIR_ITERS	int	3	The maximum number of iterations for global antenna repairs.
GRT_OVERFLOW_ITERS	int	50	The maximum number of iterations waiting for the overflow to reach the desired value.
GRT_ANTENNA_REPAIR_MARGIN	int	10	The margin to over fix antenna violations.
GRT_ANTENNA_REPAIR_JUMPER_ONLY	bool	False	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.
GRT_ANTENNA_REPAIR_DIODE_ONLY	bool	False	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.
DESIGN_REPAIR_BUFFER_INPUT_PORTS	bool	True	Specifies whether or not to insert buffers on input ports when design repairs are run.
DESIGN_REPAIR_BUFFER_OUTPUT_PORTS	bool	True	Specifies whether or not to insert buffers on input ports when design repairs are run.
DESIGN_REPAIR_REMOVE_BUFFERS	bool	False	Invokes OpenROAD’s remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets.
VERILOG_POWER_DEFINE	Optional	USE_POWER_PINS	Specifies the name of the define used to guard power and ground connections in the output Verilog header.
ERROR_ON_PDN_VIOLATIONS	bool	True	Checks for unconnected nodes in the power grid. If any exists, an error is raised at the end of the flow.
MANUAL_GLOBAL_PLACEMENTS	Optional	-	A dictionary of instances to their global (non-legalized and unfixed) placement location.
CTS_BALANCE_LEVELS	Optional	-	Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).
CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT	Optional	-	Controls automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value.The value of 100 means no derating of max cap limit
CTS_DELAY_BUFFER_DERATE_PCT	Optional	-	This option balances latencies between macro cells and registers by inserting delay buffersThe value of 100 means all needed delay buffers are inserted
CTS_OBSTRUCTION_AWARE	Optional	-	Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.
CTS_SINK_CLUSTERING_ENABLE	bool	True	Enables pre-clustering of sinks to create one level of sub-tree before building the H-tree. Each cluster is driven by a buffer which becomes the end point of the H-tree structure.
CTS_SINK_CLUSTERING_SIZE	Optional	-	Specifies the maximum number of sinks per cluster.
CTS_SINK_CLUSTERING_MAX_DIAMETER	Optional	-	Specifies the maximum diameter of the sink cluster.
CTS_MACRO_CLUSTERING_SIZE	Optional	-	Specifies the maximum number of sinks per cluster for the macro tree.
CTS_MACRO_CLUSTERING_MAX_DIAMETER	Optional	-	Specifies the maximum diameter of the sink cluster for the macro tree.
CTS_CLK_MAX_WIRE_LENGTH	Decimal	0	Specifies the maximum wire length on the clock net.
CTS_DISABLE_POST_PROCESSING	bool	False	Specifies whether or not to disable post cts processing for outlier sinks.
CTS_DISTANCE_BETWEEN_BUFFERS	Decimal	0	Specifies the distance between buffers when creating the clock tree.
CTS_CORNERS	Optional	-	Clock tree synthesis step-specific override for PNR_CORNERS.
CTS_ROOT_BUFFER	str	-	Defines the cell inserted at the root of the clock tree. Used in CTS.
CTS_CLK_BUFFERS	List	-	Defines the list of clock buffer names or buffer name wildcards to be used in CTS.
CTS_MAX_CAP	Optional	-	Overrides the maximum capacitance CTS characterization will test. If omitted, the capacitance is extracted from the lib information of the buffers in CTS_CLK_BUFFERS.
CTS_MAX_SLEW	Optional	-	Overrides the maximum transition time CTS characterization will test. If omitted, the slew is extracted from the lib information of the buffers in CTS_CLK_BUFFERS.
CTS_APPLY_NDR	Literal	half	Applies 2X spacing non-default rule to clock nets except leaf-level nets following some strategy. There are four strategy options: ‘none’, ‘root_only’, ‘half’, ‘full’.
DRT_THREADS	Optional	-	Specifies the number of threads to be used in OpenROAD Detailed Routing. If unset, this will be equal to your machine’s thread count.
DRT_OPT_ITERS	int	64	Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute.
DRT_SAVE_SNAPSHOTS	bool	False	Experimental: saves an odb snapshot of the layout each routing iteration. This increases disk usage considerably but is useful for debugging.
DRT_ANTENNA_REPAIR_ITERS	int	3	The maximum number of iterations to run antenna repair. Set to a positive integer to attempt to repair antennas and then re-run DRT as appropriate.
DRT_ANTENNA_REPAIR_MARGIN	int	10	The margin to over fix antenna violations.
DRT_ANTENNA_REPAIR_JUMPER_ONLY	bool	False	Only use jumpers to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_DIODE_ONLY.
DRT_ANTENNA_REPAIR_DIODE_ONLY	bool	False	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_JUMPER_ONLY.
DRT_SAVE_DRC_REPORT_ITERS	Optional	-	Write a DRC report every N iterations. If DRT_SAVE_SNAPSHOTS is enabled, there is an implicit default value of 1.
NON_DEFAULT_RULES	Optional	-	Specify non-default rules. Can be used to change the width, spacing and vias of a net.
DRT_ASSIGN_NDR	Optional	-	Specify which nets should be assigned to which non-default rule. The net name is a regular expression. Use ‘^name$’ to match an exact name.
ERROR_ON_TR_DRC	bool	True	Checks for DRC violations after routing and exits the flow if any was found.
IGNORE_DISCONNECTED_MODULES	Optional	-	Modules (or cells) to ignore when checking for disconnected pins.
ERROR_ON_DISCONNECTED_PINS	bool	True	Checks for disconnected instance pins after detailed routing and quits immediately if so.
ERROR_ON_LONG_WIRE	bool	True	Checks if any wire length exceeds the threshold set in the PDK. If so, an error is raised at the end of the flow.
WIRE_LENGTH_THRESHOLD	Optional	-	A value above which wire lengths generate warnings.
FABULOUS_OPTIMISATION_WIDTH_STEP_COUNT	int	4	The number of placement sites by which the tile size reduces in each iteration. The actual reduction in DBU is this count multiplied by the PDK site dimensions.
FABULOUS_OPTIMISATION_HEIGHT_STEP_COUNT	int	1	The number of placement sites by which the tile size reduces in each iteration. The actual reduction in DBU is this count multiplied by the PDK site dimensions.
FABULOUS_OPT_MODE	OptMode	balance	Optimisation mode to use. Options are: - ‘find_min_width’: default, finds minimal width by increasing from initial guess. - ‘find_min_height’: finds minimal height by increasing from initial guess. - ‘balance’: finds minimal area by starting from square bounding box and increasing alternatingly. - ‘no-opt’: Disable optimisation.
IGNORE_ANTENNA_VIOLATIONS	bool	False	If True, antenna violations are ignored during tile optimisation. Default is False.

Tile VHDLMacro Flow Classic

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
FABULOUS_IGNORE_DEFAULT_DIE_AREA	bool	False	When is true will ignore the provided die area and use the default one instead.

Tile Verilog Macro Flow

Variable	Type	Default	Description
RUN_TAP_ENDCAP_INSERTION	bool	True	Enables the OpenROAD.TapEndcapInsertion step.
RUN_POST_GPL_DESIGN_REPAIR	bool	True	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.
RUN_POST_GRT_DESIGN_REPAIR	bool	False	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.
RUN_CTS	bool	True	Enables clock tree synthesis using the OpenROAD.CTS step.
RUN_POST_CTS_RESIZER_TIMING	bool	True	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.
RUN_POST_GRT_RESIZER_TIMING	bool	False	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.
RUN_HEURISTIC_DIODE_INSERTION	bool	False	Enables the Odb.HeuristicDiodeInsertion step.
RUN_ANTENNA_REPAIR	bool	True	Enables the OpenROAD.RepairAntennas step.
RUN_DRT	bool	True	Enables the OpenROAD.DetailedRouting step.
RUN_FILL_INSERTION	bool	True	Enables the OpenROAD.FillInsertion step.
RUN_MCSTA	bool	True	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.
RUN_SPEF_EXTRACTION	bool	True	Enables parasitics extraction using the OpenROAD.RCX step.
RUN_IRDROP_REPORT	bool	True	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.
RUN_LVS	bool	True	Enables the Netgen.LVS step.
RUN_MAGIC_STREAMOUT	bool	True	Enables the Magic.StreamOut step to generate GDSII.
RUN_KLAYOUT_STREAMOUT	bool	True	Enables the KLayout.StreamOut step to generate GDSII.
RUN_MAGIC_WRITE_LEF	bool	True	Enables the Magic.WriteLEF step.
RUN_KLAYOUT_XOR	bool	True	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.
RUN_MAGIC_DRC	bool	True	Enables the Magic.DRC step.
RUN_KLAYOUT_DRC	bool	True	Enables the KLayout.DRC step.
RUN_EQY	bool	False	Enables the Yosys.EQY step. Not valid for VHDLClassic.
RUN_LINTER	bool	True	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.
FABULOUS_IGNORE_DEFAULT_DIE_AREA	bool	False	When is true will ignore the provided die area and use the default one instead.